网站旧版 | 学校首页 | 中文版 | English

胡昱

作者: 时间:2017-03-08 点击数:

姓 名:胡昱

职称:教授(青年千人)

专业方向:微电子工程系

个人简介:

职称:教授、博士生导师

研究所(实验室):微电子工程系

武汉智慧城市研究院院长,青年千人

电话: +86-27-81889933

Email: huyu.cs@gmail.com

学习工作经历:

胡昱,男,1980年9月出生,华中科技大学光学与电子信息学院教授,博士生导师,武汉智慧城市研究院院长。曾任加拿大阿尔伯塔大学电子与计算机工程系任助理教授、博士生导师。他先后在清华大学计算机系获得学士和硕士学位,在美国加州大学洛杉矶分校(UCLA)电子工程系获得博士学位,毕业后留校进行博士后研究工作半年。胡昱博士的研究方向包括:物联网相关的前沿技术(包括数字信号处理、云计算信息平台和数据挖掘等)、超大规模集成电路(VLSI)设计、电路与系统的体系结构。他主持或作为主要成员参与了以下重要单位资助的数十项研究课题,包括:加拿大自然科学与工程研究理事会(NSERC),中国国际人才交流协会和加拿大科学技术合作中心(ISTP-Canada)、美国国家科学基金委(National Science Foundation)、美国半导体研究协会(SRC)、中国国家865高科技重点项目和973基础科学研发项目等等。他曾获得清华大学优秀毕业生奖;在可编程逻辑电路上的创新研究获得了2008年美国电气和电子工程师协会设计自动化会议(IEEE Electronic Design Automation Council)的最佳贡献奖;从2008年到2010年3年连续在国际集成电路计算机辅助设计会议(International Conference on Computer-Aided Design)和国际设计自动化(Design Automation Conference)上获得最佳论文提名。他获得美国发明专利2项、国家发明专利4项;在国际重要研究期刊和会议上发表学术论文50余篇(其中被SCI索引收录文章10余篇);其研究成果被国际学者引用过两百次(截止2010年)。胡博士在相关领先国际上发言近20次,并3次被两家大型可编程逻辑器件公司邀请作学术演讲;他现任若干美国电气和电子工程师协会(IEEE)和美国计算机协会(Association of Computing Machinery, 简称ACM)学术期刊的特邀审稿人。主要研究方向、领域:物联网应用技术、嵌入式系统、可重构计算、可编程逻辑(FPGA)、超大规模集成电路设计工具。

研究方向、领域:

物联网应用技术、嵌入式系统、可重构计算、可编程逻辑(FPGA)、超大规模集成电路设计工具

主要成果:

近期主要奖励:

2012年入选第三批国家“青年千人计划”。

2008年、2009年、2010年:关于“可容错”FPGA的从2008年到2010年研究连续三年获得国际会议ICCAD和DAC的最佳论文提名(ICCAD和DAC会议是EDA方面的顶级国际会议,论文录取率低于20%)。

2008年,为具有EDA工业标准之称的Open Access系统开发了一整套FPGA的前端综合工具,这项成果于2008年在美国Lake Tahoe 举行的国际逻辑综合大会(IWLS)上,被美国美国电气和电子工程师协会(IEEE)的设计自动化委员会(Council on Electronic Design Automation)颁发了“最佳贡献奖”。此奖项为会议的最高奖项。

近期发表的部分学术论文:

[1]. Lei He, Shauki Elassaad, Yiyu Shi, Yu Hu, Wei Yao, "System-in-Package: Electrical and Layout Perspectives", Foundations and Trends in Electronic Design Automation .vol.4 no.4, pp. 223-306 2011.

[2]. Wenyao Xu, Jia Wang, Yu Hu, Ju-Yueh Lee, Fang Gong, Lei He, Majid Sarrafzadeh, "In-Place FPGA retiming for mitigation of variational single-event transient faults", IEEE Transactions on Circuits and Systems Part I (TCAS-I), Vol.58, Jun, 2011, pp. 1372 –1381.

[3]. Chun Zhang, Yu Hu, Lingli Wang, Lei He and Jiarong Tong, “Accelerating Boolean Matching Using Bloom Filter”, IEICE Transactions, Vol.E93-A,No.10,Oct. 2010. pp.1775-1781.

[4]. Yu Hu, Satyaki Das, Steve Trimberger and Lei He, Design and Synthesis of Programmable Logic Block with Mixed LUT and Macro-Gate, IEEE TCAD, 2009, 28(4), pp. 591-595.

[5]. Yu Hu, Victor Shih, Rupak Majumdar and Lei He, Exploiting Symmetries to Speed-Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs, IEEE Transactions on Computer-Aided Design for Circuits and Systems, 2008, 27(10), pp.1751-1760.

[6]. King Ho Tam, Yu Hu, Lei He, Tong Jing and Xinyi Zhang, Dual Vdd Buffer Insertion for Power Reduction, IEEE Transactions on Computer-Aided Design for Circuits and Systems, 2008, 27(8), pp. 1498-1502.

[7]. Yu Hu, Yan Lin, Lei He and Tim Tuan, Physical Synthesis for FPGA Interconnect Power Reduction by Dual-Vdd Budgeting and Retiming, ACM Transactions on Design Automation for Circuits and Systems, 13, 2 (Apr. 2008), pp. 1-29.

[8]. Pengfei Zhu, Chun Zhang, Hua Li, Ray Cheung and Yu Hu, An FPGA-Based Acceleration Platform for Auction Algorithm, ISCAS 2012. (accepted for publication)

[9]. Tianyun Zhang, Rui Zhang, Lingli Wang, Yu Hu, A Method to Build Reconfigurable Architectures by Extracting. Common Subgraphs. ASICON 2011. pp.1043-1046.

[10]. Lintao Cui, Jing Chen, Yu Hu, Jinjun Xiong, Zhe Feng and Lei He, Acceleration of Multi-agent Simulation on FPGAs, FPL 2011. pp. 470 –473.

[11]. Zhe Feng, Naifeng Jing, Yu Hu, and Lei He, IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-based FPGAs, FPL 2011. pp. 482 –485.

[12]. Xiaoyu Shi, Dahua Zeng, Yu Hu, Osmar Zaiane and Guohui Lin, Enhancement of Incremental Design for FPGAs Using Circuit Similarity, ISQED, 2011, pp. 1-8.

[13]. Chun Zhang, Yu Hu, Lingli Wang, Lei He and Jiarong Tong, Engineering a Scalable Boolean Matching Based on EDA SaaS 2.0, ICCAD, 2010, pp. 750 –755.

[14]. Manu Jose, Yu Hu and Rupak Majumdar, On Power And Fault-Tolerant Optimization In FPGA Physical Synthesis, ICCAD, 2010, pp. 224 –r29.

[15]. Manu Jose, Yu Hu, Rupak Majumdar and Lei He, Rewiring for Robustness, DAC, 2010, pp. 469 - 474. (最佳论文提名,607篇投稿中共有9篇被提名最佳论文)

[16]. Samuel Luckenbill, Ju-Yueh Lee, Yu Hu, Rupak Maju-dar, and Lei He, RALF: Reliability Analysis for Logic Faults - An Exact Algorithm and Its Applications, DATE, 2010, pp. 783 - 788.

[17]. Chun Zhang, Yu Hu, Lei He, Lingli Wang and Jiarong Tong, Building A Faster Boolean Matcher Using Bloom Filter, FPGA, 2010, pp. 185-188.

[18]. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, and Minming Li, Fault-Tolerant Resynthesis for Dual-Output LUTs, ASP-DAC, 2010, pp. 325 - 330.

[19]. Lei He and Yu Hu, Power-Efficient and Fault-Tolerant Circuits and Systems, ASICON, 2009, pp. 708 - 713. (特邀论文)

[20]. Zhe Feng, Yu Hu, Lei He and Rupak Majumdar, IPR: In-Place Reconfiguration for FPGA Fault Tolerance, ICCAD, 2009, pp. 105 - 108. (最佳论文提名,438篇投稿中共有12篇被提名最佳论文)

[21]. Ju-Yueh Lee, Yu Hu, Rupak Majumdar, and Lei He, Simultaneous Test Pattern Compaction, Ordering and X-Filling for Testing Power Reduction, IEEE International Symposium on Quality Electronic Design (ISQED), 2009, pp. 702-707.

[22]. Wei Yao, Yiyu Shi, Lei He, Sudhakar Parmati and Yu Hu, "Worst Case Timing Jitter and Amplitude Noise in Differential Signaling", ISQED, 2009., pp. 40-46.

[23]. Yu Hu, Zhe Feng, Rupak Majumdar, and Lei He, Robust FPGA Resynthesis Based on Fault Tolerant Boolean Matching, ICCAD, 2008, pp. 706-713. (最佳论文提名,458 篇投稿中共有9篇被提名最佳论文)

[24]. Yu Hu, Victor Shih, Rupak Majumdar, and Lei He, FPGA Area Reduction by Multi-Output Function Based Sequential Resynthesis, DAC, 2008. pp. 24-29.

部分专利:

[1]. Satyaki Das and Yu Hu, Balancing logic resource usage in a programmable integrated circuit, 美国专利7636907

[2]. Satyaki Das and Yu Hu, Methods of balancing logic resource usage in a programmable logic device, 美国专利7788624.

办公地点:西一楼101室

Title: Professor of Electrical Engineering

Phone: +86-27-81889933

Email: huyu.cs@gmail.com

Dr. Yu Hu is a professor of School of School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan, China, the director of Wuhan Research Institute for Smarter Cities and an elective expert of 1000 Young Talent Plan of China. Prior to that, he was an Assistant Professor at the Department of Electrical and Computer Engineering at University of Alberta, Edmonton, Canada. He received his B. Eng. and M. Eng. both from the Department of Computer of Computer Science and Technology at Tsinghua University and his Ph.D. from the Department of Electrical Engineering at University of California, Los Angeles.

Dr. Hu’s research interests include cyber-physical systems, data processing and data mining, computer-aided design for integrated circuits and systems. He has been the PI for research projects with over CAN$ one million financial support. His research has been funded by agents including Natural Science Foundation of China (NSFC) and Natural Sciences and Engineering Research Council (NSERC) of Canada. The Wuhan Research Institute for Smarter Cities, which he is currently directing, is the official research facility funded by the Wuhan local government as a platform to incubate innovation of the smarter-city applications.

Dr. Hu has published over 50 research papers and received three best paper award nominations from top conferences in the field, including IEEE/ACM Design Automation Conference (DAC) 2010 and IEEE/ACM International Conference on Computer-Aided Design (ICCAD) 2009 and 2008. He also received the best contribution award from IWLS 2008 IEEE programming challenge.

Academic Degrees

PhD in Electrical Engineering, Department of Electrical Engineering, University of California, Los Angeles

M.Eng, Computer Science and Technology, Tsinghua University, 2005

B.Eng, Computer Science and Technology, Tsinghua University, 2002

Professional Experience

At Huazhong University of Science and Technology since 2012, School of Optical and Electronic Information, Professor (2012-present);

At University of Alberta since 2010, Department of Electrical and Computer Engineering, University of Alberta, Assistant Professor (2010-2012);

Work Experience[a1]

· 2012/09-present, School of Optical and Electronic Information, Huazhong University of Science and Technology

· Professor

· 2012/8-present, Wuhan Research Institute for Smarter Cities

· Director

· 2010/1-2012/7, Department of Electrical and Computer Engineering, University of Alberta

· Assistant Professor

· 2009/06-2009/12 Department of Electrical Engineering, University of California, Los Angeles

· Post-doctoral researcher

· 2005/09-2009/05 Department of Electrical Engineering, University of California, Los Angeles

· Research Assistant

· 2006/06-2006/09 Xilinx Research Lab.

Professional Activities[a2]

· Publicity Chair

Ø Applied Reconfigurable Computing Symposium (ARC) 2012

· TPC member

Ø Applied Reconfigurable Computing Symposium (ARC) 2012

Ø International Conference on Computer Design (ICCD) 2011, 2012

Ø International Conference on Field-Programmable Technology (FPT) 2010

· Session chair

Ø Universal Village Conference 2012

Ø Design Automation Conference (DAC) 2010

· Reviewer

Ø IEEE Transactions on Computers

Ø IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD)

Ø IEEE Transactions on Circuits and Systems I/II (TCAS)

Ø ACM Transactions on Design Automation of Electronic Systems (TODAES).

Ø IEEE/ACM Design Automation Conference (DAC)

Ø IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

Ø IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

Ø IEEE/ACM International Symposium on Field Programmable Gate Array (ISFPGA)

Ø IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC).

Research Grants (totally over CAN$ 1,000,000 in the past 3 years)[a3]

· PI, 1000 Talent Plan Startup Grant, China Central Government, the Organization Department of the Central Committee of the CPC, RMB 4,000,000, 2012-2015

· PI, FPGA Acceleration for Graph-based Data Mining, Natural Science Foundation of China (NSFC), RMB 800,000, 2013-2016

· PI, Startup Grant, University of Alberta, CAN$75,000, 2010-2011

· PI, Discovery Grant: Robust Synthesis for Nano-scale FPGAs, funded by Natural Sciences and Engineering Research Council (NSERC) of Canada, CAN$ 26,000 x 5 years

· PI (Co-PIs: Bruce Cockburn, Jie Han and Vincent Gaudet), Organization of International Workshop on Emerging Circuits and Systems, funded by Canada International Science and Technology Partnerships, CAN$ 20,000, 2010-2011

· PI (Co-PIs: Osmar Zaiane and Ray Cheung), Acceleration Engine for Graph-based Data Mining Using GPUs, equipment domination (two Tesla C2050) worth $7000, 2010-2011

· Co-PI (PI: Osmar Zaiane), Harvesting Human Power for Audio Transcribing By an Online Game, Alberta Ingenuity Centre for Machine Learning (AICML), CAN$ 8,000, 2010/05-2010/09

Selected Publications

· SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. Integration, the VLSI Journal, 46(1): 22-32 (2013)

· System-in-Package: Electrical and Layout Perspectives, Foundations and Trends in Electronic Design Automation .vol.4 no.4, pp. 223-306 2011.

· In-Place FPGA retiming for mitigation of variational single-event transient faults, IEEE Transactions on Circuits and Systems Part I (TCAS-I), Vol.58, Jun, 2011

· Accelerating Boolean Matching Using Bloom Filter, IEICE Transactions, Vol.E93-A,No.10,Oct. 2010.

· Providing a Cushion for Wireless Healthcare Application Development, IEEE Potentials Magazine,2010, Jan./Feb. pp. 19-23.

· Design and Synthesis of Programmable Logic Block with Mixed LUT and Macro-Gate, IEEE TCAD, 2009, 28(4),pp. 591-595.

· Exploiting Symmetries to Speed-Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs, IEEE TCAD, 2008, 27(10), pp.1751-1760.

· Dual Vdd Buffer Insertion for Power Reduction, IEEE TCAD, 2008, 27(8), pp. 1498-1502.

· Physical Synthesis for FPGA Interconnect Power Reduction by Dual-Vdd Budgeting and Retiming, ACM TODAES, 13, 2 (Apr. 2008), pp. 1-29.

· Fashion: A Fast and Accurate Solution to Global Routing Problem, IEEE TCAD 2008, 27(4), pp.726-737.

· A full scale solution to the rectilinear obstacle-avoiding Steiner problem, Elsevier INTEGRATION, the VLSI Journal, 2008, 41(3), pp. 413-425.

· Lambda-OAT: Lambda-Geometry Obstacle-Avoiding Tree Construction with O (nlogn) Complexity. IEEE TCAD, 26(11), 2007, pp. 2073-2079.

· ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm, Journal of Computer Science & Technology, 2006, 21(1), pp. 147-152.

· FORst: A 3-Step Heuristic for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction. Journal of Information & Computational Science, 2004, 1(3), pp. 107-116.

· (Show more..)

Patents[a4]

· Balancing logic resource usage in a programmable integrated circuit, US Patent 636907

· Methods of balancing logic resource usage in a programmable logic device, US Patent 7788624

· A method for obstacle-avoiding routing tree construction with good wire-length performance. (Chinese patent pending 200410090885.5. published on 2005/04/06), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng, and Yang Yang.

· A method for obstacle-avoiding rectilinear Steiner minimum tree construction. (Chinese patent 200410069118.6, granted), By Xianlong Hong, Tong Jing, Yu Hu, Zhe Feng, and Yang Yang.

· A method for timing-driven global routing considering coupling effects. (Chinese patent 03124095.X, granted) By Xianlong Hong, Tong Jing, Jingyu Xu, Ling Zhang, and Yu Hu.

· A method for standard cell global routing considering crosstalk reduction. (Chinese patent 02156622.4, granted) By Xianlong Hong, Tong Jing, Jingyu Xu, Ling Zhang, and Yu Hu.

Working Papers

· 1576R: The Role of Culture in the Resolution of Information Incongruity: Additivity versus Attenuation

Selected Cases

· M321: Obama and the Power of Social Media and Technology[a5]

Awards and Honors

· Distinguished Scientific Achievement Award, 2014, Society for Consumer Psychology (SCP)

· Selected into the 1000 Young Talent Plan by the Organization Department of the Central Committee of the CPC, 2012

· Best paper award nominations

· Design Automation Conference 2010 (1%)

· International Conference on Computer-Aided Design 2009 (2%)

· International Conference on Computer-Aided Design 2008 (2%)

· Best contribution award from IWLS 2008 IEEE programming challenge

· UCLA Research Assistant Fellowship, 2007-2009

· Outstanding Graduate Student from Tsinghua University, 2005

Courses Taught

· Processor Architecture

· Embedded System

Centers/Programs

  • Director of Wuhan Research Institute for Smarter Cities


Academic Areas:cyber-physical systems,

data processing and data mining, computer

-aided design for integrated circuits and systems

华中科技大学  光学与电子信息学院  联系电话:027-87558726  邮编:430074 地址:中国•湖北省武汉市珞喻路1037号 华中科技大学南五楼六楼